Analyst Ming-Chi Kuo has echoed different studies that Apple is predicted to make use of a brand new chip packaging expertise within the A20 chip, which is able to debut within the iPhone 18 subsequent yr. His report focuses on suppliers for chip packaging supplies, reasonably than the advantages of the brand new course of. We heard the identical from analyst Jeff Pu a pair months in the past.
Once you purchase an iPhone 16 as we speak, the A19 chip inside is a fairly large and sophisticated monolithic “system on a chip.” It’s bought the CPU, GPU, Neural Engine, video and audio encoders and decoders, and a bunch of different little stuff all on one huge advanced piece of silicon with round 30 billion transistors. Many chips are made on an enormous silicon disk (known as a wafer) after which packaged up and lower into particular person A19 chips, known as “dies.”
However the RAM shouldn’t be on the identical piece of silicon. RAM is usually manufactured utilizing completely different silicon processes, on completely different huge wafers, lower into their very own dies. Then the RAM is mixed with the massive SoC by connecting the 2 collectively utilizing one other piece of silicon, known as an interposer.
That is achieved as a result of the manufacturing processes that produces SRAM effectively is completely different than what produces logic effectively. However with a brand new TSMC expertise known as “Wafer-Degree Multi-Chip Module (WMCM) packaging,” which may all change.
This course of will make it attainable for Apple to construct an enormous monolithic chip that contains the RAM on the identical die because the CPU, GPU, Neural Engine, media encoders, and so forth. If the present rumors are appropriate, this may be 12GB of RAM, however the course of doesn’t require any certain amount. Rumors level to the iPhone 18 as the primary machine to make use of the brand new chip, and the iPhone Fold is also a candidate.
On-die RAM could simplify the manufacturing course of, requiring fewer steps than the present RAM-on-interposer setup. However the profit for customers is the potential to have very vast and quick RAM interfaces, making entry to RAM virtually as quick as a high-level SRAM cache. This might drastically enhance efficiency in conditions which might be restricted by reminiscence bandwidth, similar to high-performance 3D graphics or sure AI purposes.
It might additionally permit for higher energy administration, permitting the SoC with built-in RAM to make use of much less energy than the present setup with RAM connected on an interposer. This will likely enhance battery life, however battery life is an element of many alternative elements just like the show, wi-fi radios, storage, and extra.
